Following on from my last post on building logic gates from NPN transistors, I’ve now designed the XOR gate needed to build our Full Adder. As can be seen in the screen shot below, the top circuit shows an XOR gate built using 4 NAND gates and the second circuit shows the same XOR circuit built using 8 NPN transistors.

XOR Gate Built Using NPN Transistors

As Always, copy and paste the following code into the free Java Circuit Simulator to get a feeling for the design.

$ 1 5.0E-6 1.500424758475255 50 5.0 50
151 432 160 544 160 0 2 5.0
151 544 112 656 112 0 2 5.0
151 544 208 656 208 0 2 0.0
w 544 160 544 192 0
w 544 160 544 128 0
151 656 160 768 160 0 2 5.0
w 656 112 656 144 0
w 656 176 656 208 0
w 432 96 432 144 0
w 432 96 544 96 0
w 432 176 432 224 0
w 432 224 544 224 0
M 768 160 816 160 0 2.5
L 432 96 384 96 0 0 false 5.0 0.0
L 432 224 384 224 0 1 false 5.0 0.0
x 302 51 840 57 0 24 XOR Using Combinational Logic (NAND Gates)
x 284 341 866 347 0 24 XOR Using Combinational Logic (NPN Transistors)
R 320 576 288 576 0 0 40.0 5.0 0.0 0.0 0.5
R 320 624 288 624 0 0 40.0 5.0 0.0 0.0 0.5
t 448 576 480 576 0 1 -4.769244679759966 0.09853954879251582 100.0
t 448 624 480 624 0 1 0.5721119236721417 0.572360682090304 100.0
w 480 592 480 608 0
r 400 576 448 576 0 10000.0
r 400 624 448 624 0 10000.0
s 320 576 368 576 0 1 false
s 320 624 368 624 0 0 false
r 480 512 480 560 0 100.0
R 480 512 448 512 0 0 40.0 5.0 0.0 0.0 0.5
g 480 640 480 656 0
g 368 672 368 688 0
r 368 624 368 672 0 10000.0
w 480 560 512 560 0
w 656 448 688 448 0
r 576 512 576 560 0 10000.0
g 576 560 576 576 0
g 656 528 656 544 0
R 656 400 624 400 0 0 40.0 5.0 0.0 0.0 0.5
r 656 400 656 448 0 100.0
r 576 512 624 512 0 10000.0
r 576 464 624 464 0 10000.0
w 656 480 656 496 0
t 624 512 656 512 0 1 0.5713598382462943 0.5716085966689409 100.0
t 624 464 656 464 0 1 -4.875710385258664 0.09853954878803152 100.0
t 624 688 656 688 0 1 -0.11894285435755281 0.6683177341910094 100.0
t 624 736 656 736 0 1 0.5011262498555432 0.6685976279719069 100.0
w 656 704 656 720 0
r 576 688 624 688 0 10000.0
r 576 736 624 736 0 10000.0
r 656 624 656 672 0 100.0
R 656 624 624 624 0 0 40.0 5.0 0.0 0.0 0.5
g 656 752 656 768 0
g 576 784 576 800 0
r 576 736 576 784 0 10000.0
w 656 672 688 672 0
w 512 560 528 560 0
w 528 560 528 512 0
w 528 512 576 512 0
w 528 560 528 688 0
w 528 688 576 688 0
t 784 576 816 576 0 1 0.554942286102126 0.6083225786232598 100.0
t 784 624 816 624 0 1 -1.2089972951264762 0.607048116653794 100.0
w 816 592 816 608 0
r 736 576 784 576 0 10000.0
r 736 624 784 624 0 10000.0
r 816 512 816 560 0 100.0
R 816 512 784 512 0 0 40.0 5.0 0.0 0.0 0.5
g 816 640 816 656 0
g 736 672 736 688 0
r 736 624 736 672 0 10000.0
w 688 448 688 576 0
w 688 576 736 576 0
w 688 672 688 624 0
w 688 624 736 624 0
162 864 560 864 640 1 2.1024259 1.0 0.0 0.0
w 816 560 864 560 0
w 864 640 816 640 0
w 400 464 400 576 0
w 400 464 576 464 0
w 400 624 400 736 0
w 576 736 400 736 0
w 368 624 400 624 0
w 368 576 400 576 0